So, according to the block diagram... there's 3.3v and 1.05v going in.... I wonder if they're using a charge pump to generate the 5v for the usb port, or if they ommitted it in the diagram, or if it's not actually there.
OK, I appreciate that the 5v could be wired directly to the port, but the block diagram specifically mentions the port power control interface... maybe it's to enable the requests for more power and it interfaces with external power limiting hardware.
You mention that USB3 is back-compatible with USB2, as I expected. However, USB2 is back-compatible with USB1. Not knowing much about the inner workings of USB - will USB1 devices work on USB3 ports?
Port power control block is also marked as being external to the chip, so I'd guess at the chip controls the power without routing the power THROUGH the chip.
IMHO, it would be pretty wasteful to put 5V through silicon simply to forward on to the physical ports, so I figure that voltage would be hardwired. But someone correct me if I'm wrong.
USB power is (almost?) always switched externally to the controller chip. Processes suitable for this high speed stuff don't make good, cheap, high current FETs. (Also, cheap manufacturers want to do the power control on the cheap, with (resettable) fuses, no current monitoring, no shutdown.
USB 3.0 is backward compatible with USB 1.1 - that's, in part, what the USB 2.0 element is for.
The cabling's compatible too: USB 3.0 ports will interconnect with USB 1.1/2.0 connectors. Some, but not all, will work the other way round, but USB 3.0 device plugged into USB 2.0 port will only connect at 480Mb/s peak, not 5Gb/s.
I saw a diagram (possibly on here) which showed the USB3.0 socket as physically compatible with USB2.0/1.1 but with a small extension to the plug so you can plug a USB2.0 plug into a USB3.0 socket and it only meets up with USB2.0 compatible pins, but the 3.0 plug fits in further to pick up the faster data transfer pins.
So it's a full implementation of USB2.0 (including 1.1 which is part of the 2.0 spec) plus extra pins for the faster connection.
Of course it could all have changed since I last looked!
All there for you in black and white on the drawing. There are separate USB3 and USB2 PHYs, with the USB2 PHY handling the High Speed / Full Speed / Low Speed (i.e. USB2, USB 1.1, USB 1) traffic.
So yes, a USB3 port will be able to interface with a piece of USB1 hardware.
Intel Core i7 I7-920 Quad Core Processor (2.66GHz, 4x256kB, 4.8GT/s QPI, LGA 1336 Socket B)
Intel Core i5 750 Qaud Core Processor (2.66GHz, 8MB L3 Cache, 2.5 GT/s Bus, Socket H LGA1156)
Intel Core i7 Extreme Edition I7-975 Quad Core Processor (3.33GHz, 8MB L3 Cache, 4x512KB L2 Cache, 6.4 GT/s, Socket B LGA 1336)
Asus P7P55D Motherboard (Intel Socket H LGA1156, P55 Express, ATX, 16GB DDR3)
AMD Phenom II X4 965 Quad Core Processor (3.4GHz, 6MB L3 Cache, 4x512KB L2 Cache, 4000 MT/s Bus, Socket AM3)
Anonymous Coward
Voltage #
Posted Tuesday 19th May 2009 13:22 GMT
So, according to the block diagram... there's 3.3v and 1.05v going in.... I wonder if they're using a charge pump to generate the 5v for the usb port, or if they ommitted it in the diagram, or if it's not actually there.
OK, I appreciate that the 5v could be wired directly to the port, but the block diagram specifically mentions the port power control interface... maybe it's to enable the requests for more power and it interfaces with external power limiting hardware.
Glad to see USB3 is getting there though.
Greg
Backwards compatibility #
Posted Tuesday 19th May 2009 14:49 GMT
You mention that USB3 is back-compatible with USB2, as I expected. However, USB2 is back-compatible with USB1. Not knowing much about the inner workings of USB - will USB1 devices work on USB3 ports?
Simon Neill
@Voltage #
Posted Tuesday 19th May 2009 14:49 GMT
Port power control block is also marked as being external to the chip, so I'd guess at the chip controls the power without routing the power THROUGH the chip.
Anonymous Coward
Port Voltage #
Posted Tuesday 19th May 2009 14:49 GMT
IMHO, it would be pretty wasteful to put 5V through silicon simply to forward on to the physical ports, so I figure that voltage would be hardwired. But someone correct me if I'm wrong.
Anonymous Coward
USB voltage #
Posted Tuesday 19th May 2009 14:49 GMT
USB power is (almost?) always switched externally to the controller chip. Processes suitable for this high speed stuff don't make good, cheap, high current FETs. (Also, cheap manufacturers want to do the power control on the cheap, with (resettable) fuses, no current monitoring, no shutdown.
Robert
Ha this is sweet #
Posted Tuesday 19th May 2009 14:49 GMT
Nice
Tony Smith, Editor, Reg Hardware
@Greg #
Posted Tuesday 19th May 2009 15:40 GMT
USB 3.0 is backward compatible with USB 1.1 - that's, in part, what the USB 2.0 element is for.
The cabling's compatible too: USB 3.0 ports will interconnect with USB 1.1/2.0 connectors. Some, but not all, will work the other way round, but USB 3.0 device plugged into USB 2.0 port will only connect at 480Mb/s peak, not 5Gb/s.
Chris O'Shea
If I remember correctly ... #
Posted Tuesday 19th May 2009 15:40 GMT
I saw a diagram (possibly on here) which showed the USB3.0 socket as physically compatible with USB2.0/1.1 but with a small extension to the plug so you can plug a USB2.0 plug into a USB3.0 socket and it only meets up with USB2.0 compatible pins, but the 3.0 plug fits in further to pick up the faster data transfer pins.
So it's a full implementation of USB2.0 (including 1.1 which is part of the 2.0 spec) plus extra pins for the faster connection.
Of course it could all have changed since I last looked!
Anonymous Coward
5v, 3.3v #
Posted Tuesday 19th May 2009 15:47 GMT
G E E K ! ! ! !
Paris - she know about high speed
Adam Foxton
@Greg #
Posted Tuesday 19th May 2009 15:47 GMT
All there for you in black and white on the drawing. There are separate USB3 and USB2 PHYs, with the USB2 PHY handling the High Speed / Full Speed / Low Speed (i.e. USB2, USB 1.1, USB 1) traffic.
So yes, a USB3 port will be able to interface with a piece of USB1 hardware.
Greg
Cheers guys #
Posted Wednesday 20th May 2009 10:17 GMT
Ah, so that's what HS/FS/LS was. Cheers.
This forum is now closed for new posts.